Week In Review: Design, Low Power
Cadence will NUMECA International, a provider of computational fluid dynamics (CFD), mesh generation, multi-physics simulation, and optimization solutions for industries including aerospace, automotive, industrial, and marine.
“Next-generation products and systems require comprehensive multi-physics engineering solutions encompassing IP, semiconductors, IC packaging, modules, boards, complex mechanical structures and more,” said Tom Beckley, senior vice president and general manager of the Custom IC & PCB Group at Cadence. “With the addition of NUMECA’s technology to the Cadence portfolio, we are broadening our system analysis capabilities and integrated design solutions, addressing critical customer challenges in areas such as internal and external flows, acoustics, heat transfer, fluid-structure interaction and optimization.” Founded in 1993 as a spin-off of the Vrije Universiteit Brussel (VUB), NUMECA is based in Brussels, Belgium. Terms of the deal were not disclosed. It is expected to close in the first quarter of 2021.
Silvaco Polyteda Cloud, which provides tools for rapid physical verification of IC designs prior to mask creation and manufacturing and for cloud enablement of EDA tools.
“IC designers are looking for design-rule-check/layout-versus-schematic (DRC/LVS) tools that provide quick run-times, compatibility with their current design flow, and can take advantage of server farms to divide-and-conquer the largest verification tasks,” said Thomas Blaesi, vice president and general manager, EDA Division at Silvaco. “The Polyteda technology provides all of this and more. We look forward to bringing this versatile physical verification solution to design teams worldwide.” Polyteda was founded in 2015 and is based in Kyiv, Ukraine.
Tools & IP
Ansys HFSS Mesh Fusion for fully-coupled simulation of complex electromagnetic systems. HFSS Mesh Fusion allows for combination of IC, packaging, connectors, printed circuit boards, antennas, and platform in a single analysis to predict EM interactions. It applies optimal meshing technology at the component level, parallelized across cores, clusters or within Ansys Cloud, and solver technology then extracts a fully coupled, uncompromised, full-wave EM matrix. Samsung Electronics and Herrick Technology Labs noted they are using the tool.
Aldec its Active-HDL IDE to support new features within VHDL-2019 (IEEE 1076-2019). These features simplify the language, lift certain restrictions that were present in earlier versions and introduce new APIs. Support has also been added for release 2020.08 of the open-source VHDL verification methodology (OSVVM). Active-HDL includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for FPGA designs.
PLDA XpressLINK-SOC CXL IP with full support for the AMBA CXS Issue B (CXS-B) interface protocol. AMBA CXS is a credit-based streaming protocol that enables high-bandwidth transmission of packets between a user application and the protocol controller. CXS provides reduced latency by allowing the controller’s transaction layer to be bypassed and aims to make it easier to implement the CXL and CCIX multichip interconnect standards in Arm-based SoCs.
Faraday Technology a complete imaging and display high-speed interface IP set on UMC’s 40LP and 28HPC/HPC+ process nodes, including MIPI D-PHY (TX/RX, controller), V-by-One HS (TX/RX, controller), and LVDS (TX/RX, I/O). The IP are PPA optimized for applications such as 4K/8K projectors, automotive HUD and infotainment, AR/VR, and surveillance cameras.
Arasan Chip Systems eMMC PHY IP for TSMC’s 22nm ULP and ULL processes. The eMMC PHY IP is integrated with Arasan’s eMMC 5.1 Host Controller IP and Software.
Deals & Certifications
Sondrel Synopsys’ Fusion Design and Verification Continuum platforms for the design and verification of large, complex SoC designs for automotive, AI, machine learning, IoT, consumer AR/VR gaming, and security applications. Sondrel plans to replace its legacy design systems and cited a track-record of power-efficient designs and power, performance, and area metrics.
Siemens verification tools for analog/mixed-signal circuits were for early design starts on Samsung Foundry’s new 3nm Gate All Around (GAA) process technology. The Analog FastSPICE platform is now enabled in Samsung Foundry’s device models and design kits.
R&D spending by semiconductor companies is to grow 4% in 2021 to $71.4 billion after rising 5% in 2020 to a record high of $68.4 billion, predicts market research firm IC Insights. Ten companies made up 64% of the industry’s total R&D spending.
Qualcomm’s market share in China dropped last year, falling to 25.4% in 2020 versus 37.9% in 2019. The company’s shipments in China dropped 48.1%, and CINNO Research, with a major factor being the blocking of component shipments to Huawei. Instead, MediaTek is taking up greater position in Chinese-made smartphones, with recent deals reportedly placing it in Oppo, Vivo, Xaiomi, and Huawei devices.
Find a new conference or learning opportunity at our , or check out an upcoming .
Si2 will host a workshop on efforts to assess AI capacity and infrastructure, as well as application of AI for semiconductor test, on Jan. 29.
In February, the 2021 International Solid-State Circuits Virtual Conference will be held Feb. 13-22. The International Symposium on Field-Programmable Gate Arrays will take place Feb. 28-Mar. 2.
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